| 摘要 |
A PLL circuit that includes a sampled phase detector, a filter and a voltage-controlled oscillator (VCO) is disclosed. The sampled phase detector compares an incoming reference signal, Vref, and the output of the VCO, VO, to generate an error signal, Ierr, representing the phase difference between the reference signal, Vref, and the VCO output, VO. The error signal, Ierr, is filtered by a low pass filter and applied to the VCO to produce an output signal, VO, that tracks the phase of the reference signal, Vref. Jitter is reduced by reducing the delay between the sampled phase detector and the VCO. Delay is reduced by utilizing short current pulses, as opposed to the continuous charge-pump current produced by conventional sampled phase detectors. The sampled phase detector injects all the charge-pump current into the VCO at once, reducing the delay by up to half of a clock cycle. In a further implementation, the total delay in the feedback loop is reduced by applying a charge output current, Ierr, that is known to be required within a predefined period of time. An additional charge injection can be applied to the VCO each time the phase error value is zero, for the anticipated oscillation period until the next zero crossing. Thus, short pulses charge current, Ierr, are initially injected into the low pass filter following a zero crossing, to inject a similar charge for the estimated duration of the oscillation period, until the next zero crossing is predicted to occur.
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