发明名称 Integrated circuit bonding pads including closed vias and closed conductive patterns
摘要 Multilayer bonding pads for integrated circuits include first and second spaced apart conductive patterns and a dielectric layer therebetween. A closed conductive pattern is included in the dielectric layer that electrically connects the first and second spaced apart patterns. The closed conductive pattern encloses an inner portion of the dielectric layer and is enclosed by an outer portion of the dielectric layer. The closed conductive pattern may be a circular, elliptical, polygonal or other conductive pattern. A second closed conductive pattern may also be included in the inner portion of the dielectric layer, electrically connecting the first and second spaced apart conductive patterns. An open conductive pattern having end points, may also be included in the dielectric layer. The open conductive pattern may be included in the inner portion of the dielectric layer, in the outer portion of the dielectric layer or both. Bonding pads may be formed by forming a dielectric layer on an integrated circuit substrate, the dielectric layer including the closed via therein that encloses an inner portion of the dielectric layer and is enclosed by an outer portion of the dielectric layer. A conductive pattern is formed in the closed via and on the dielectric layer opposite the substrate. The conductive pattern preferably fills the closed via. The steps of forming a dielectric layer and forming a conductive pattern may be repeatedly performed, to form a multilayer bonding pad on the integrated circuit substrate.
申请公布号 US6222270(B1) 申请公布日期 2001.04.24
申请号 US19980103970 申请日期 1998.06.24
申请人 SAMSUNG ELECTRONICS CO., LTD. 发明人 LEE HYAE-RYOUNG
分类号 H01L21/768;H01L21/60;H01L23/485;(IPC1-7):H01L23/48;H01L23/52;H01L29/40 主分类号 H01L21/768
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