发明名称 Bus bridge architecture for a data processing system capable of sharing processing load among a plurality of devices
摘要 The method and apparatus provides a data processing system. The data processing system includes a primary bus, a secondary bus, and a host processor connected to the primary bus. The data processing system includes a first secondary processor connected to the primacy bus and the secondary bus. Additionally, a second secondary processor is connected to the secondary bus. The first secondary processor and the second secondary processor forms cascaded processors for input/output functions. Selected functions normally performed by the second secondary processor are performed by the first secondary processor, wherein a division of workload increases performance of the data processing system. This architecture allows shifting of workload down to the secondary bus.
申请公布号 US6223240(B1) 申请公布日期 2001.04.24
申请号 US20000494477 申请日期 2000.01.31
申请人 LSI LOGIC CORPORATION 发明人 ODENWALD LOUIS;SCHREMMER STEVE
分类号 G06F13/40;(IPC1-7):G06F13/00 主分类号 G06F13/40
代理机构 代理人
主权项
地址