| 摘要 |
A microprocessor includes a multiply-accumulate unit (MAU) for performing high-speed signal processing operations. First and second caches provide first and second operands (x, y) directly to the MAU when a multiply-accumulate (MAC) instruction is executed. In addition, a multiplexer is included to select data from either the first and second caches when a normal instruction is executed. A translation look-aside buffer may be included that has page table entries that include additional "reconfigure" and "way" bits to control writing data into the caches. In this manner, the microprocessor may use a conventional n-way set-associative cache to simultaneously access two or more operands.
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