| 摘要 |
In order to improve verification performance for the cell hierarchy in a gate array LSI layout, and accurately, efficiently verify the hierarchy at a high speed, this invention relates to a hierarchy verification method and apparatus for an LSI layout in which, in verifying the cell hierarchy in the gate array LSI layout, input gate array LSI layout data is divided into a top cell data portion and a function block cell data portion, the top cell data portion is mapped while leaving only a wiring figure in an underlying cell, an underlying cell of the function block cell data portion that is pasted while maintaining a relative positional relationship with a laid function block cell is mapped, and each figure layout of the cell hierarchy is verified using the obtained top cell data and function block cell data.
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