| 摘要 |
It is an object of the invention to provide a synchronizing circuit which prevents an occurrence of an unexpected output data caused by latching an input signal on a course of a transition thereof. An input signal Si is represented as a binary data having a width of three bits which increases by "1" every clock, and encoded into a signal having a width of eight bits. The encoded signal having the width of eight bits is latched and restarted synchronizing with a clock (CLK1) by a F/F circuit and another F/F circuit operating in accordance with an asynchronous clock (CLK2). The output signal of the F/F circuit is decoded into a signal having a width of three bits by the decoder, and outputted as an output signal So. Since an encoder is provided, the data before or after a transition can be correctly outputted, even when the data is latched by the F/F circuit on a course of the transition.
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