Method and apparatus for analyzing performance and density of a source design module for a target programmable gate array

摘要

A method and apparatus for analyzing performance and density of a source design module for a target programmable gate array. The source design module is converted to logic for a selected target programmable gate array. Performance and density of the converted logic are then estimated. If the estimated performance level does not achieve a target performance level, then problematic design elements are automatically or optionally converted to functionally equivalent programmable gate array design elements. The performance and density of the target programmable gate array is again estimated using the new design elements. In another mode of operation, design guidance is provided in converting the problematic design elements.