| 摘要 |
The present invention utilizes a cache which stores various decoded instructions, or parcels, so that these parcels can be made available to the execution units without having to decode a microprocessor instruction, such as a CISC instruction, or the like. This increases performance by bypassing the fetch/decode pipeline stages on the front end of the microprocessor by using a parcel cache to store previously decoded instructions. The parcel cache is coupled to the microprocessor fetch/decode unit and can be searched during an instruction fetch cycle. This search of the parcel cache will occur in parallel with the search of the microprocessor instruction cache. When parcel(s) corresponding to the complex instruction being fetched are found in the parcel cache a hit occurs and the corresponding micro-ops are then sent to the execution units, bypassing the previous pipeline stages. The parcel cache is dynamic and will use a replacement algorithm, such as least recently used, to determine how long the parcels will remain in the cache.
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