发明名称 WIRING FORMATION METHOD
摘要 PROBLEM TO BE SOLVED: To provide a method for forming wiring wherein the erosion of a low-k (low dielectric constant) film in a process for forming an embedded wiring can be prevented. SOLUTION: When a polysilicon is used as the material of a lower-layer wiring 102, a side-wall deposit 118a comprising Si is formed on the side wall of a via hole 110 by sputtering on the surface of a lower-layer wiring 102 in a via hole formation process S5. The side-wall deposit 118a is oxidized with oxygen ion at O2-RIE in a resist film removing process S6, to become an SiO2 film. An SiO2 is hard to erode by a WF6. Thus, in an embedded wiring formation process S8, the side-wall deposit 118a prevents, together with a protective film 112, erosion of the low-k film 104.
申请公布号 JP2001110899(A) 申请公布日期 2001.04.20
申请号 JP19990292341 申请日期 1999.10.14
申请人 OKI ELECTRIC IND CO LTD 发明人 YOSHIE TORU
分类号 H01L21/302;H01L21/768;H01L23/522;(IPC1-7):H01L21/768 主分类号 H01L21/302
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