| 摘要 |
PROBLEM TO BE SOLVED: To prevent erroneous write-in when noise is inputted to a write-enable signal. SOLUTION: Relating to DRAM timing generator 24 provided with a WS signal generating circuit 241 activating a write-state signal WS responding to activation of a write-enable signal/WE, a DE signal generating circuit 244 activating a write-driver-enable signal DE responding to activation of a WS signal, further, the device is provided with a driver reset circuit 242 activating a driver-reset signal/DRES1 responding to non-activation of a WE signal, and gives a signal/DRES1 to a NAND circuit 24431 after a flip-flop circuit 2441 in the DE signal generating circuit 244.
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