INTERMITTENT OPERATION CONTROL CIRCUIT FOR PLL SYNTHESIZER

摘要

PROBLEM TO BE SOLVED: To provide a PLL synthesizer intermittent operation control circuit capable of quickly driving an internal circuit after resetting a power saving state. SOLUTION: When a phase difference between a reference signal FRAR and a comparing signal FPAR falls within prescribed time, a 1st reset signal generation circuit 32 in the intermittent operation control circuit 31 generates a 1st internal power save reset signal PSRS1. A 2nd reset signal generation circuit 33 detects the output signal of a comparing frequency divider 22 or a reference frequency divider 23 and generates a 2nd internal power save reset signal PSRS2. A priority circuit 34 gives priority to an earlier signal out of the 1st and 2nd internal power save reset signals PSRS1, PSRS2 and generates a power save reset signal PSRS for resetting the power saving state of the internal circuit by the priority signal.