| 摘要 |
PROBLEM TO BE SOLVED: To reduce a manufacturing cost of a tester using a tester having lower speed than an operation frequency of a LSI or to reduce overhead for chip area of a BIST circuit. SOLUTION: A tester 10 operated with speed of half of an operation frequency of a LSI 12 inputs data 1, 2 into input pins 24, 25 synchronously with a clock of the tester 10. A parallel-serial converting circuit 27 in a RAM test logic circuit 13 converts inputted data to serial data switched by a clock of the LSI 12, and writes it in a RAM 14 by a clock of the LSI in order of data 1, data 2. A RAM test logic circuit 15 reads out the data 1 and the data 2 written in the RAM 14 synchronously with a clock of the LSI 12. A serial- parallel converting circuit 30 writes the read out data 1, 2 in a tester 17 by outputting alternately the data 1, 2 to output pins 31, 32 so as to be switched by the tester 17. The tester 17 compares read out data with an expected value and extracts fault of the RAM 14. Operation speed of the tester 10 may be 1/t of the LSI 12.
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