发明名称 ARITHMETIC AND CONTROL UNIT AND STATUS MONITOR AND CONTROL EQUIPMENT USING THE UNIT
摘要 PROBLEM TO BE SOLVED: To correct a data error or the like even when the number of bits of data to be processed by a central processing unit(CPU) 14 is '4', '8', '16' or the like. SOLUTION: A main storage device 21 is constituted of a data storage part 37 for storing data obtained from the CPU 14, a correction code generation part 35 for generating a correction code for data outputted from the CPU 14, a correction code storage part 38 for storing the correction code generated by the generation part 35, and a correction execution part 39 for calculating a collation syndrome on the basis of the correction code read out from the storage part 38 at the time of reading out data stored in the storage part 37 to the CPU 14, judging whether there is an error in the read data or not by the collation syndrome, and when there is an error in a prescribed condition, correcting the error and outputting the corrected data. Consequently the reliability of data can be improved.
申请公布号 JP2001111435(A) 申请公布日期 2001.04.20
申请号 JP19990283800 申请日期 1999.10.05
申请人 TOSHIBA CORP 发明人 ITAGAKI DAIKI;FUWA YUTAKA;NAGASAKI HIROMI
分类号 G06F11/10;G06F12/16;H02H3/02;H02H3/28;H03M13/01;H03M13/19;H04L1/00 主分类号 G06F11/10
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