| 摘要 |
<p>PROBLEM TO BE SOLVED: To reduce a circuit scale by removing the limit of an input pulse width, and simplifying the constitution. SOLUTION: Delay circuits DL11-DL16 delay the 'H→L edge' of an input signal, and non-inversion output it. The N pieces of delay circuits DL11-DL13 are serially connected so that a first delay part for delaying the tail edge of an input pulse in a prescribed time, and for outputting it can be constituted. A first inverting circuit IV11 inverts the output of the delay circuit DL13 in the final stage of the first delay part. The N pieces of delay circuits DL14-DL16 are serially connected so that a second delay part for delaying the leading edge of the pulse inverted by the first inverting circuit IV11 in the prescribed time, and for outputting it can be constituted. A second inverting circuit IV12 inverts the output of the delay circuit DL16 in the final stage of the second delay part, and outputs it.</p> |
