| 摘要 |
PROBLEM TO BE SOLVED: To suppress the sudden frequency variation of an output clock even when the phase of a clock inputted to a PLL circuit is suddenly changed. SOLUTION: A comparator 6 compares the output voltage of a phase comparator 1 for generating voltage proportional to a detected phase difference with an optionally set voltage value. A delay circuit 7 inserts a phase delay into an output clock from a VCO 5 on the basis of an output result from the comparator 6 and outputs the clock to a phase comparator 2. The comparator 2 can suppress the variation of control voltage of the VCO 5 obtained by the addition voltage of the loops of the 1st and 2nd phase comparator 1, 2 because the phase of the comparator 2 itself is controlled in the reverse direction of the phase of the comparator 1. Consequently variation in the frequency of the output clock can be eased. |
