发明名称 ADJUSTABLE BANDWIDTH PHASE LOCKED LOOP WITH FAST SETTLING TIME
摘要 An adjustable bandwidth phase-locked loop (100) including a phase-locked loop having a first input node receiving an input signal (114) having a first frequency, a second input node receiving a feedback signal (116) and an output node (118) which has a signal indicative of an error signal characterizing a frequency error between the input signal and the feedback signal. The adjustable bandwidth phase-locked loop includes a voltage controlled oscillator (130), coupled to the second input node, receiving the error signal and generating the feedback signal where the feedback signal has a frequency which tracks the first frequency. The adjustable bandwidth phase-locked loop includes a variable loop filter (120, 135, and 140), coupled between the phase-locked loop and the voltage controlled oscillator, filtering the error signal. The variable loop filter is configurable to allow for the tracking of the input signal over both of a broad bandwidth and a narrow bandwidth.
申请公布号 WO0101577(A8) 申请公布日期 2001.04.19
申请号 WO1999US18249 申请日期 1999.08.11
申请人 DENSO INTERNATIONAL AMERICA, INC.;KIRKPATRICK, JAMES, B. 发明人 KIRKPATRICK, JAMES, B.
分类号 H03L7/093;H03L7/095;H03L7/10;H03L7/107;H03L7/113;(IPC1-7):H03L7/187;H03L7/00 主分类号 H03L7/093
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