Clock generator makes output clock signals and main clock signal undergo phase adjustment after frequencies of feedback clock signals and reference clock pulses are equalized

摘要

The clock signals output by the dividers (361,363) are received together with a reset signal (RST) by the dividers (331,341) which output feedback clock signals to phase locked loops (PLL) (310,320). The frequencies of the feedback clock signals and reference clock pulses are equalized, making the output clock signals and the main clock signal (HCLK) undergo phase adjustment. The dividers (332,342) receive the main clock signal and the reset signal and output reference clock pulses to the corresponding PLLs. The dividers (351-353) receive the reset signal and a clock signal from the PLLs and output clock signals which are received by the dividers (361,363) together with the reset signal. An Independent claim is also included for a clock generating method.