| 摘要 |
<p>A multi-level memory (10) in which each storage cell stores multiple bits. The memory includes a plurality of storage words (11-13), a data line (50) and a plurality of reference lines (51-53), and a read circuit (40). Each storage word (11-13) includes a data memory cell and a plurality of reference cells. Each memory cell includes an isolation transistor (19) and a storage element (15-18) having first and second terminals for storing a charge. The stored charge determines a conductivity value measurable between the first and second terminals. The isolation transistor (19) is connected to the first terminal and connects the first terminal to one of the lines (50-53). The first terminal of the data memory cell is connected to the data line (50), and the first terminal of each of the reference memory cells is connected to a corresponding one of the reference lines (51-53) when the isolation transistors are in a conducting state. The isolation transistors are placed in the conducting state by a signal on a word line (21-23) connected to each of the isolation transistors in the storage word (11-13).</p> |
