Assembly for generating a consecutive count

摘要

An assembly for generating a consecutive count includes an n-stage binary counter (24) incrementable by counting pulses in successive cycles and an EEPROM (10) in which an item of information representing the count achieved in each case is stored in the pauses between the cycles. The EEPROM (10) comprises n+1 memory cells. A control circuit (36) is provided causing the contents of the n-1 stages of the binary counter (24) assigned to the most-significant bits to be stored in the n-1 first memory cells of the EEPROM (10) and the contents of the n or (n+1) memory cell is changed in alternate cycles. On commencement of each cycle the contents of the n-1 first memory cells of the EEPROM (10) is transferred into the corresponding stages of the binary counter (24) and a bit is written into the n stage of the binary counter (24) formed by linking the contents of the n and (n+1) memory cells of the EEPROM (10) such that the count corresponds to the count attained in the previous cycle, whereby the counting pulse then increments the binary counter (24) to the next count.