| 摘要 |
The address generation circuit 10 generates the address in which the fail data is stored. The logical circuit 15 comprises: when the address is inputted, a circuit to delay the address by a predetermined constant time; a circuit to output the selection signal which is the binary level signal; and a circuit to output the signal inputted from the address generation circuit 10 or the signal inputted from the pipe line circuit, corresponding to the value of the selection signal. When the address is inputted, the memory array 16 outputs the fail data stored in the address of the memory units A -D, or writes the inputted fail data in address of the memory units A -D. The OR circuit 70 OR-operates a plurality of inputted fail data, and outputs to the memory array 16.
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