| 摘要 |
An integrated circuit includes a substrate (12) having a conductive region (18), and includes a dielectric layer (19) disposed over the substrate. An upwardly tapering frustoconical opening (22) is created through the dielectric layer to the conductive region. A barrier layer (31) is then applied, after which a thin metal layer (32) is applied, the upper end of the opening being pinched off or closed by the metal layer. Heat and pressure are then simultaneously applied, so that the metal layer flows to completely fill the available space within the opening. Selected portions of the metal layer external to the opening are then etched away. A further dielectric layer (41) is applied over the barrier layer and metal layer, and then planarization is carried out on the further dielectric layer.
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