| 摘要 |
RAM cells having a substantially balanced number of N-MOS and P-MOS transistors are disclosed. In a two-port RAM cell the invention uses an N read-write port comprising N-MOS transistors and a P read-port comprising P-MOS transistors. In a three-port RAM cell having one read-write port, the invention adds another N read-port comprising N-MOS transistors to the same two-port RAM cell. In effect, for each read-port added to a RAM cell, the invention alternates between a P read-port and then an N read-port. In a RAM cell having multiple N read-write-ports and multiple read-ports, the invention selects the number of P read-ports and/or the number of N read-ports such that the number of N-MOS transistors in the RAM cell are substantially the same as the number of P-MOS transistors. The invention is thus advantageous over the prior art because the invention provides a more balanced number of N-MOS and P-MOS transistors in each RAM cell, which better utilizes the layout areas. In accordance with the invention, using an N-read port to read data from a RAM cell pre-charges the corresponding bit lines to a high logic state. Conversely, using a P read-port to read data pre-charges the bit lines to a low logic state. |
