发明名称 |
False exception for cancelled delayed requests |
摘要 |
A central processor uses virtual addresses to access data via cache logic including a DAT and ART, and the cache logic accesses data in the hierarchical storage subsystem using absolute addresses to access data, a part of the first level of the cache memory includes a translator for virtual or real addresses to absolute addresses. When requests are sent for a data fetch and the requested data are not resident in the first level of cache the request for data is delayed and may be forwarded to a lower level of said hierarchical memory, and a delayed request may result in cancellation of any process during a delayed request that has the ability to send back an exception. A delayed request may be rescinded if the central processor has reached an interruptible stage in its pipeline logic at which point, a false exception is forced clearing all I the wait states while the central processor ignores the false exception. Forcing of an exception occurs during dynamic address translation (DAT) or during access register translation (ART). A request for data signal to the storage subsystem cancellation is settable by the first hierarchical level of cache logic. A false exception signal to the first level cache is settable by the storage subsystem logic.
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申请公布号 |
US6219758(B1) |
申请公布日期 |
2001.04.17 |
申请号 |
US19980047579 |
申请日期 |
1998.03.24 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
NAVARRO JENNIFER ALMORADIE;KRUMM BARRY WATSON;SHUM CHUNG-LUNG KEVIN;MAK PAK-KIN;FEE MICHAEL |
分类号 |
G06F12/08;G06F12/10;(IPC1-7):G06F12/00 |
主分类号 |
G06F12/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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