发明名称 |
Semiconductor device with delay locked loop |
摘要 |
A semiconductor device capable of easily adjusting an internal delay time is provided with a phase adjusting circuit, wherein the phase adjusting circuit comprises an internal delay reproduction circuit that reproduces the sum of a delay time required for an input signal to be input to the phase adjusting circuit and a delay time required for an output signal to be output from the phase adjusting circuit. A delay adjusting circuit connected with the internal delay reproduction circuit upstream or downstream relative thereto, generates a given delay time for adjusting the internal delay time reproduced by the internal delay reproduction circuit. A delay time control section is connected with the delay adjusting circuit and controls the delay time generated by the delay adjusting circuit. A phase comparator compares a phase of a signal passed through the delay time adjusting circuit with a signal inputted to the phase adjusting circuit. A delay selection circuit generates a given delay time for allowing a phase of the signal passed through the delay adjusting circuit to coincide with a phase of the signal inputted to the phase adjusting circuit, based on an output of the phase comparator.
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申请公布号 |
US6218877(B1) |
申请公布日期 |
2001.04.17 |
申请号 |
US19990316037 |
申请日期 |
1999.05.21 |
申请人 |
OKI ELECTRIC INDUSTRY CO., LTD. |
发明人 |
OYAMA KAZUHIKO;KAWANO HIROAKI |
分类号 |
H01L27/04;G06F1/10;G11C11/407;H01L21/82;H01L21/822;H03K5/13;H03L7/081;(IPC1-7):H03L7/06 |
主分类号 |
H01L27/04 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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