| 摘要 |
One embodiment of the present invention provides a computer system that maintains status information for several peripheral devices in a status register, which is located within a core logic unit in the computer system. In this embodiment, a peripheral device updates the status register if its status changes by performing a bus master operation to transfer status information to the status register. It then generates an interrupt to indicate to a processor that it requires servicing. When the processor services the interrupt, the processor merely has to read the status register to determine which peripheral device requires processing. This is a very fast operation because the status register is internal to the core logic. No time-consuming polling of peripheral devices is required to determine the status of the peripheral devices. Thus, one embodiment of the present invention provides an apparatus within a core logic device that maintains status information for peripheral devices in a status register. This apparatus includes a peripheral communication channel coupled to a number of peripheral devices. An updating circuit is located within the core logic unit and is coupled between the peripheral communication channel and the status register. This updating circuit includes a mechanism to update the status register in response to signals containing status information received from the peripheral devices through the peripheral communication channel.
|
