发明名称 |
Apparatus and method for extracting circuit, system and method for generating information for simulation, and netlist |
摘要 |
A circuit extracting apparatus or method of the present invention extracts circuit information which allows a drain current and a gate capacitance in an actual device to be reproduced with high fidelity in circuit simulation. Transistor-portion-configuration recognizing means recognizes the configuration of a transistor portion in the mask layout of a semiconductor circuit so as to generate transistor-portion-configuration data. Transistor-size calculating means calculates an equivalent transistor size based on the transistor-portion-configuration data, such that a drain current in the circuit simulation coincides with the drain current in the actual device. Corrective-capacitance generating means obtains the difference between a gate capacitance in the circuit simulation using the equivalent transistor size and the gate capacitance in the actual device so as to virtually generate a corrective capacitance having a capacitance value corresponding to the obtained difference. The equivalent transistor size and the corrective capacitance serve as the circuit information in the circuit simulation.
|
申请公布号 |
US6219630(B1) |
申请公布日期 |
2001.04.17 |
申请号 |
US19960758868 |
申请日期 |
1996.12.02 |
申请人 |
MATSUSHITA ELECTRONICS CORPORATION |
发明人 |
YONEZAWA HIROKAZU;UMEDA TAKUYA;ISHIKURA SATOSHI |
分类号 |
G06F17/50;(IPC1-7):G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|