| 摘要 |
Structures and methods for programmable memory decode circuits are provided with logic cells, or floating gate transistors, which can operate with lower applied control gate voltages than conventional memory decode circuits. The programmable logic arrays of the present invention do not increase the costs or complexity of the fabrication process. According to the teachings of the present invention, the floating gate capacitance in the logic cells is much smaller than the control gate capacitance such that the majority of any voltage applied to the control gate will appear across the floating gate thin tunnel oxide. The memory decode circuits include a number of address lines and a number of output lines such that the address lines, and the output lines form an array. A number logic cells are disposed at the intersections of output lines and address lines. A number of non volatile memory cells are disposed at the intersections of the address lines and at least one redundant output line. The number of non volatile memory cells include a source region, a drain region, and channel region separating the source and the drain regions in a horizontal substrate. A first vertical gate is located above a portion of the channel region and separated from the channel region by a first thickness insulator material. A second vertical gate is located above another portion of the channel region and separated therefrom by a second thickness insulator material.
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