发明名称 SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD
摘要 PURPOSE: To obtain a semiconductor device which can be lessened in parasitic capacitance produced between the pad of a gate electrode and a body region, where the semiconductor device is a DTMOS(dynamic threshold voltage MOSFET) where an SOI substrate is employed. CONSTITUTION: The electrode 6NA of a gate electrode 6N is formed on the upper surface of an SOI layer 4 through the intermediary of a gate insulating film 5N in the element forming region of an SOI substrate 1. The pad 6NB of a gate electrode 6N is formed on an element isolation insulating film 9 in the element isolation region of the SOI substrate 1. A contact hole 11N is formed selectively penetrating through an interlayer insulating film 10 and the element isolation insulating film 9 between the upper surface of the interlayer insulating film 10 and the upper surface of the SOI layer 4. The side wall of the pad 6NB of the gate electrode 6N is brought into contact with a W plug 21 plugged into the contact hole 11N.
申请公布号 KR20010030243(A) 申请公布日期 2001.04.16
申请号 KR20000051844 申请日期 2000.09.02
申请人 MITSUBISHI DENKI KABUSHIKI KAISHA 发明人 HIRANO YUICHI
分类号 H01L27/08;H01L21/762;H01L21/84;H01L27/12;H01L29/78;H01L29/786;(IPC1-7):H01L29/78 主分类号 H01L27/08
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