| 摘要 |
PURPOSE: A multiple differential pair transistor architecture having transconductance proportional to bias current for any transistor technology is provided to realize a multiple differential pair circuit having a transconductance, gm, proportional to the bias current. CONSTITUTION: A multiple differential pair circuit is disclosed having a transconductance, gm, proportional to the bias current, I0, for any transistor technology. The transistors utilized to construct each of the differential transistor pairs in a multiple differential pair circuit are permitted to have a non-exponential voltage-current (V-I) characteristic. As multiple differential pair circuits are linearized, the effective transconductance, gm, becomes (i) linearly dependent on bias current, and (ii) insensitive to the voltage-current (V-I) characteristics of the utilized devices. Methods and apparatus are disclosed that provide a linear transconductance, gm, with respect to the bias current, I0, using differential pairs of transistors where each transistor has a non-exponential voltage-current (V-I) characteristic, such as MOS transistors.
|
