| 摘要 |
<p>PURPOSE: To provide a DLL circuit used suitably as a circuit for generating the internal clock of a semiconductor storage, including DDR-SDRAM. CONSTITUTION: A DLL circuit 100 is equipped with clock input buffers 110 and 115 that generates mutually complementary internal signals which are synchronized with an external clock signal, a delay circuit 120 that composes a delay loop arranged between the clock input buffer 110 and a phase difference control circuit 150, the phase difference control circuit 150 for setting delay control time, so that the phase of a signal through the delay loop matches the phase of one of the internal signals, a delay circuit 125 for giving delay control time being commonly set with the delay circuit 120 to the other of the internal signals, and a pulse generation circuit 160 for generating an internal clock signal, in response to the output signal of the delay circuits 120 and 125.</p> |
