发明名称 POWER REDUCING CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a power reduction circuit that activates a low load circuit by reducing power consumed by transistors(TRs). SOLUTION: Current flowing through a TR 4 from its collector to its emitter activates a drive circuit 5 to apply a voltage across a Zener diode 6 to apply a constant voltage to the emitter of the TR 4. This constant voltage is applied to the low load circuit 7, which consumes power.
申请公布号 JP2001103332(A) 申请公布日期 2001.04.13
申请号 JP19990275194 申请日期 1999.09.28
申请人 NEC HOME ELECTRONICS LTD 发明人 YOSHIDA HIDEKI
分类号 H04N3/16;G09G1/00;G09G1/04;(IPC1-7):H04N3/16 主分类号 H04N3/16
代理机构 代理人
主权项
地址