| 摘要 |
PROBLEM TO BE SOLVED: To provide a method and a device for multiplication which can decrease the circuit scale and make the operation speed fast by minimizing the constitution other than a multiplier which is added so as to multiply multiplicand data having a larger bit width than the multiplier in use by multiplier data. SOLUTION: Input data sX and sY consisting of 32-bit signed integers are handled so that the high-order blocks of high-order 16 bits are integers with sign sXH and sYH and the low-order blocks of low-order 16 bits are unsigned integers uXL and uYL; and their partial product data Dp1 to Dp4 (uXL×uYL, sXH×uYL, uXL×sYH, sXH×sYH) are added while having place matching to find multiplication result data sZ. This multiplying method eliminates the need to convert the data type of input data X and Y and multiplication result data Z (with sign to without sign or vice versa), so the device is made small- sized and the process is made fast.
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