| 摘要 |
PROBLEM TO BE SOLVED: To provide a fail memory circuit and its interleave copying method suppressing the processing time for interleave copying to the minimum. SOLUTION: An address generating circuit 10 generates an address in which fail data are stored. A logic circuit 15 is constituted of a circuit delaying the address by the prescribed fixed time when an address is inputted, a circuit outputting a selection signal being a binary level signal, and a circuit outputting a signal inputted from the address generating circuit 10 or a signal inputted from a pipeline circuit in accordance with a value of a selection signal. A memory array 16 outputs fail data stored in the address of memory units A-D when an address is inputted or writes inputted fail data in the address of the memory units A-D. A OR circuit 70 takes OR of inputted plural fail data and outputs them to the memory array 16.
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