发明名称 SHIFT REGISTER AND ELECTRONIC EQUIPMENT
摘要 PROBLEM TO BE SOLVED: To shift a signal to a poststage without attenuating the level of an output signal and to prevent destruction and a malfunction caused by the parasitic capacity of a transistor. SOLUTION: This device is constituted by connecting stages consisting of TFT 21-25, 31. The TFTY 21 is turned on by a control signal from a terminal Φ, and makes a capacitor A accumulate electric charges by inputting an output signal (high level) of the preceding stage from a terminal IN. Thereby, the TFT 22, 24 are turned on, the TFT 25 is turned off, a clock signal from a terminal c1k is made a high level, then, this signal is outputted from a terminal OUT through the TFT 24 as an output signal of the stage. At the time, a potential of the capacitor A is raised by that parasitic capacity of the TFT 24 is charged. When an output signal of the preceding stage inputted to a terminal IN is varied to a low level, as a potential of the capacitor A is divided by the THT 31, voltage between a drain and a source of the TFT 21 is suppressed to the fixed value or less.
申请公布号 JP2001101889(A) 申请公布日期 2001.04.13
申请号 JP19990273198 申请日期 1999.09.27
申请人 CASIO COMPUT CO LTD 发明人 MOROSAWA KATSUHIKO;KANBARA MINORU
分类号 G11C19/28;G11C19/00 主分类号 G11C19/28
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