| 摘要 |
PROBLEM TO BE SOLVED: To easily realize a synchronous semiconductor memory operating in operation modes of a single data rate and a double data rate while using a common chip. SOLUTION: A memory array is divided into two memory cell mats (4a, 4b) and when this memory operates in the operation mode of the single data rate, these cell mats are respectively used as an upper-order bit data storage area and a lower-order bit data storage area and when the memory operates in the operation mode of the double data rate, they are respectively used as an even numbered column address data storage area and an odd numbered column address data storage area. |
