发明名称 METHOD FOR FABRICATION OF SEMICONDUCTOR DEVICE
摘要 PROBLEM TO BE SOLVED: To sandwich an electrode material, serving as a lower gate, at the time of wafer bonding using a wafer bonding technology. SOLUTION: A double gate field effect transistor comprises a lower gate electrode 3, a lower gate insulating film 4, a channel layer 5, a gate insulation film 7, and an upper gate electrode 8. An electrode material, serving as a lower gate 3, is sandwiched at the time of wafer bonding using a wafer bonding technology. Other process is similar to existing process for fabricating silicon integrated circuit in the fabrication of a semiconductor device, e.g. a double gate field effect transistor.
申请公布号 JP2001102590(A) 申请公布日期 2001.04.13
申请号 JP19990277444 申请日期 1999.09.29
申请人 AGENCY OF IND SCIENCE & TECHNOL;MATSUMOTO KAZUHIKO 发明人 MATSUMOTO KAZUHIKO;SAKAMOTO KUNIHIRO
分类号 H01L27/12;H01L21/02;H01L21/336;H01L29/786;(IPC1-7):H01L29/786 主分类号 H01L27/12
代理机构 代理人
主权项
地址