发明名称 |
INTERLEAVE ADDRESS GENERATING DEVICE AND INTERLEAVE ADDRESS GENERATING METHOD |
摘要 |
The column numbers and row numbers of a two-dimensional array are incremented by a counter control unit (101) a block interleave represented by the two-dimensional array and outputted as read address values. The read address values are inputted to a bit inversion unit (102) by which bit inversion is conducted. A row conversion unit (103) outputs address values corresponding to the bit inversion output values and the row numbers from the counter control unit (101) as row conversion values. A shift register (104) bit-shifts the output values of the bit inversion unit (102) and outputs the bit-shifted values as address offset values. An adder (105) adds the address offset values to the row conversion values. A value comparator (106) compares the sum values with the interleave size and outputs data within the interleave size as address values.
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申请公布号 |
WO0126235(A1) |
申请公布日期 |
2001.04.12 |
申请号 |
WO2000JP06974 |
申请日期 |
2000.10.06 |
申请人 |
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.;IKEDA, TETSUYA;YAMANAKA, RYUTARO |
发明人 |
IKEDA, TETSUYA;YAMANAKA, RYUTARO |
分类号 |
H03M13/27;(IPC1-7):H03M13/27 |
主分类号 |
H03M13/27 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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