| 摘要 |
<p>A multiprocessor computer system in which each processor being used as a target device (700) has a FIFO (first in first out) buffer (705) for receiving and storing transfer commands from a split transactional global bus (170) for later execution. The transfer commands are put in the FIFO of the target device in the order of their arrival and are taken out of the FIFO and executed by the target device in the same order. This eliminates the wasting of bus time that occurs when busy signals are sent from target devices to master devices and when transfer commands are resent from master devices to target devices. Therefore, the present invention eliminates the wasting of bus time related to transfer commands being rejected.</p> |
