| 摘要 |
<p>A semiconductor integrated circuit in which memory cells are arranged in a matrix of n lines and m columns (n and m are natural members), signal lines so provided as to correspond to the respective lines of the matrix are charged one by one in response to a write command to write the bits of the memory cells, after writing the bits of one line the next signal line is charged, and the bits of a charged line are written one by one. By providing a delay circuit, the discharging time required to discharge a parasitic capacitor is secured. After completion of the discharge, the address changes. Thus, no write error occurs.</p> |
