| 摘要 |
<p>A method and apparatus for building an integrated circuit. A description of the logical operation of a module in a hardware description language is provided, which includes annotations in the form of design directives. An interpreting process is configured to read the annotations and identify which logical and physical design tools are needed to process each module in the description, as well as the order in which to invoke the logical and physical design tools. Dependencies in the execution of the design tools on the various modules of the description are analyzed to determine where the processing of modules may be performed in parallel to optimize execution. The dependency analysis comprises, for example, the generation of a dependency graph. Further, the description and the intermediate results of the execution of the design tools are cached in memory. A current description is compared with a prior cached description to determine which modules are revised in the current description. Those execution steps that entail redundant processing of unrevised modules are bypassed, and the corresponding prior cached results are utilized in those distances.</p> |
