发明名称 |
Memory cell layout for reduced interaction between storage nodes and transistors |
摘要 |
A memory cell, in accordance with the invention, includes a trench formed in a substrate, and an active area formed in the substrate below a gate and extending to the trench. The active area includes diffusion regions for forming a transistor for accessing a storage node in the trench, the transistor being activated by the gate. The gate defines a first axis wherein a portion of the active area extends transversely therefrom, the portion of the active area extending to the trench. The trench has a side closest to the portion of the active area, the side of the trench being angularly disposed relative to the gate such that a distance between the gate and the side of the trench is greater than a minimum feature size. <IMAGE> |
申请公布号 |
EP1037280(A3) |
申请公布日期 |
2001.04.11 |
申请号 |
EP20000103617 |
申请日期 |
2000.02.21 |
申请人 |
INFINEON TECHNOLOGIES NORTH AMERICA CORP.;INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
PARK, YOUNG-JIN;RADENS, CARL J.;KUNKEL, GERHARD |
分类号 |
H01L21/8242;H01L27/108 |
主分类号 |
H01L21/8242 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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