发明名称 |
Analog signal processing circuit with noise immunity and reduced delay |
摘要 |
An improved pulse detection circuit provides for a reduced delay response and noise immunity. The pulse detection circuit includes a comparator with a biasing circuit providing first and second biasing signal states. The biasing signal states are adjustably delayed relative to the detected signal.
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申请公布号 |
US6215334(B1) |
申请公布日期 |
2001.04.10 |
申请号 |
US19990290968 |
申请日期 |
1999.04.13 |
申请人 |
GENERAL ELECTRONICS APPLICATIONS, INC. |
发明人 |
PERNYESZI JOSEPH |
分类号 |
H03K3/2893;(IPC1-7):H03K5/22 |
主分类号 |
H03K3/2893 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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