| 摘要 |
A clock generator for a PRML read channel for producing a clock signal with minimal jitter from an input signal subject to baseline wandering. The clock generator including a VGA amplifier, a low pass filter, an ADC, a baseline wander correction circuit, a timing offset detector and loop filter circuit, a DAC and a VCO. The VGA amplifier amplifies the input signal to produce a first analog signal. The low-pass filter filters the first analog signal to produce a second analog signal. The ADC converts the second analog signal into a first digital signal, operating synchronously with the clock signal. The baseline wander correction circuit reduces jitter in the clock signal caused by baseline wandering of the input signal. The baseline wander correction circuit produces a second digital signal from the first digital signal, operating synchronously with the clock signal. The second digital signal experiences substantially less baseline wandering than the first digital signal. The timing offset detector and loop filter circuit generates from the second digital signal a timing adjust signal representative of an adjustment to the clock signal. The timing offset detector also operating synchronously with the clock signal. The DAC converts the timing adjust signal into a third analog signal, operating synchronously with the clock signal. The VCO generates the clock signal in response to the third analog signal.
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