| 摘要 |
An architecture for a high-capacity high-speed synchronous dynamic random access memory (SRAM) (400) is disclosed. The SDRAM (400) includes memory cells logically arranged into a number of array banks (402a-402d). The array banks (402a-402d) each include first sub-banks (404a-404d) situated toward a first end of the SDRAM and second sub-banks (406a-406d) situated toward a second, opposing end of the SDRAM (400). Sub-bank buses (420a-420h), each of which includes a number of data I/O lines, couple each of the first sub-banks (404a-404d) to a first I/O circuit (412) situated toward the first end of the device, and couple each of the second sub-banks (406a-406d) to a second I/O circuit (414) situated toward the second end of the device. In this manner, overlap of the sub-bank buses (420a-420h) is limited toward the first and second ends of the device, eliminating the need to run data I/O lines across the device, and thus preventing a data I/O line routing bottleneck in the central portion of the SDRAM (400).
|
