发明名称 32-bit mode for a 64-bit ECC capable memory subsystem
摘要 A 32-bit mode operation for a typical 64-bit ECC memory subsystem. In 32-bit mode, each data block will have an 8-bit ECC value, which is consistent with ECC values generated for 64-bit data. This is achieved by prefixing the data with 32 zeroes. When reading out data, memory faults can be corrected and detected using ECC techniques on a zero prefixed data block that is read out of the memory. This allows a memory subsystem to be optimized for bandwidth and latency depending upon this application.
申请公布号 US6216247(B1) 申请公布日期 2001.04.10
申请号 US19980087390 申请日期 1998.05.29
申请人 INTEL CORPORATION 发明人 CRETA KENNETH C.;GARBUS ELLIOT
分类号 G11C29/00;(IPC1-7):G11C29/00 主分类号 G11C29/00
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