| 摘要 |
A method and structure for identifying disturbed memory cells within a memory cell array are provided. A test circuit consists of several cells within the memory cell array, and are coupled to the cells in the memory cell array. The test cells are also coupled to a test cell word line. During a long-write test, all word lines within the memory cell array are first deselected. The test cell word line is then selected, which causes the test cells to provide a logic high or a logic low voltage to the bit lines within the memory cell array. The voltage provided to the bit lines can be used to write test data into the memory cells or to create a write-disturb mode. The test cells can be either memory cells similar to that used in the memory cell array, or a circuit that couples a voltage source to the bit lines when activated.
|
