PHASE DETECTION CIRCUIT OF DATA TRANSMISSION UNIT

摘要

PURPOSE: A phase detection circuit of a data transmission unit is provided to detect correctly a phase error in a synchronous multiplexing apparatus. CONSTITUTION: A frequency divider(14) is used for dividing an input clock into 8 and supplying divided clocks of 256kHz to a write counter(16) and an SPC(Serial to Parallel Converter)(121). The SPC(121) is used for shifting input data according to the input clock, counting the number of the input data, and outputting converted parallel data and a bit data count value. A write counter(16) is used for counting an output of the frequency divider(14). A read counter(20) is used for counting an output clock of a multiplexer and generating a byte read value(RADR). A phase detector(181) is used for activating a phase error signal(PDO) by detecting a phase error of byte and a bit phase error.