SENSE AMPLIFICATION CIRCUIT OF SEMICONDUCTOR MEMORY DEVICE

摘要

PURPOSE: A sense amplification circuit is provided to prevent a misoperation occurred when a supply voltage and data are simultaneously applied to a sense amplifier and to increase a sensing operation speed by supplying the supply voltage to the sense amplifier at the time data are applied to a bit line. CONSTITUTION: The circuit includes the first through fourth switches(S1-S4), a pull-down portion(4), a pull-up portion(5), an equalization portion(1) and a bit line selection portion(2). The first and second switches turn on in response to the first mat selection signal and select data of the first mat. The third and fourth switches turn on in response to the second mat selection signal and select data of the second mat. The pull-down portion cuts off the data of the first mat to be applied to a bit line and a bit line bar in response to the first switching control signal applied as a low voltage for a predetermined time when the first and second switches turn on, applies a ground voltage to the bit line or the bit line bar according to a value of the data of the first mat, and applies the ground voltage to the bit line or the bit line bar according to voltages of the bit line and the bit line bar when the data of the second mat are outputted. The pull-up portion cuts off the data of the second mat to be applied to the bit line and the bit line bar in response to the second switching control signal applied as a low voltage for a predetermined time when the third and fourth switches turn on, applies the supply voltage to the bit line or the bit line bar according to a value of the data of the second mat, and applies the supply voltage to the bit line or the bit line bar according to voltages of the bit line and the bit line bar when the data of the first mat are outputted. The equalization portion equalizes a voltage of the bit line and the bit line bar in response to a bit line equalization signal. The bit line selection portion selects a predetermined bit line and bit line bar in response to a bit line selection signal.