发明名称 APPARATUS AND METHOD FOR TESTING SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide an apparatus and a method for testing a semiconductor integrated circuit which is high in observability and capable of conveniently detecting the delay failure, the degeneration failure, etc. SOLUTION: The apparatus comprises a test pattern input means 14 for inputting a test pattern for activating a bus under test of a semiconductor integrated circuit 20 to this integrated circuit, a transient current measuring means 16 for measuring a transient power current fed to the semiconductor integrated circuit during activating of the bus under test, and a failure detecting means 34 for judging the existence of a failure on the bus under test, based on the transient power current measured by the transient power current measuring means.
申请公布号 JP2001091568(A) 申请公布日期 2001.04.06
申请号 JP19990263472 申请日期 1999.09.17
申请人 ADVANTEST CORP 发明人 ISHIDA MASAHIRO;YAMAGUCHI TAKAHIRO;HASHIMOTO YOSHIHIRO
分类号 G01R31/28;G01R31/12;G01R31/26;G01R31/30;G01R31/3183;G01R31/319;(IPC1-7):G01R31/26 主分类号 G01R31/28
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