| 摘要 |
PURPOSE: A circuit for reading data at high speed is provided to perform fast data reading regardless of point of time when a column selecting signal is enabled and constantly maintain the speed of the read operation for the first data and a data since then. CONSTITUTION: The circuit for reading a data providing a bit line sense amp includes a timing generating portion(38), a column selecting portion(34), an input and output precharging portion(32) and an input and output sense amp(30). The timing generating portion is enabled in response to a clock signal and generates a column selecting signal which is disabled before a predetermined time when a next clock signal is generated. The column selecting portion is of which each drain is connected to first and second outputting nodes, consisted of PMOS transistors(MP30,MP31) of which the source is connected to an input and output line(LIO) and a complementary input and output line(LIOB) and transmits voltages of the first and second outputting nodes to the input and output line and the complementary input and output line in response to the column selecting signal. The input and output precharging portion performs precharging the input and output line pairs in response to a predetermined precharging signal which is enabled by the column selecting signal. The input and output sense amp senses and amplifies voltages of the input and output line and the complementary input and output line and outputs the amplified result.
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